1. Field of the Invention
The present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to a flash EPROM cell array that utilizes ETOX cell programming concepts in a true virtual ground, contactless array.
2. Discussions of the Prior Art
An electrically programmable read only memory (EPROM) device is a non-volatile memory integrated circuit which is used to store binary data. Power can be removed from an EPROM without loss of data. That is, upon reapplying power, the originally-stored data is retained.
In addition to its data retention capability, an EPROM can also be programmed to store new binary data. In a conventional EPROM device, reprogramming is accomplished by first exposing the EPROM to an ultra-violet (UV) light source in order to erase the old binary data. A UV-transparent lid on the packaged EPROM chip allows this erasure to occur. Following erasure, the new binary data is written into the EPROM by deactivating the chip select line and switching the EPROM's data outputs to inputs. The EPROM address inputs are then set to a starting value, the desired data is connected to the data inputs and the data is written into the EPROM cell identified by the address inputs. The address inputs are then incremented and the cycle is repeated for each cell in the EPROM array.
In an EPROM read operation, the binary data stored in the cell identified at the address inputs is connected to the chip's data output buffers. If the EPROM's chip select signal is activated, then the binary data from the selected cell is provided to the data bus.
An electrically erasable programmable read only memory (EEPROM) is a variation of the conventional EPROM design. In an EEPROM (sometimes referred to as an E.sup.2 PROM), binary data is read, written and erased electrically. A single operation erases the selected data storage cell.
More recently, so-called "flash" EPROM devices have become available. In a flash EPROM, all data cells in the array are electrically erased in a single operation.
FIG. 1 shows a portion of Intel's well-known ETOX EPROM array 10 wherein two ETOX cells 12a and 12b share one drain contact 14. FIG. 2 shows a cross-section of an individual ETOX cell 12 taken along line 2--2 (i.e. along polysilicon (poly 2) word line 16) in FIG. 1. FIG. 3 shows a cross-section of an ETOX cell 12 taken along line 3--3 (i.e. along buried N+ bit line 18) in FIG. 1.
The ETOX array 10 is based on the standard "T-shaped" ETOX cell. As shown in FIGS. 2 and 3, the ETOX cell 12 is implementated utilizing a very thin gate oxide 20 (about 100 .ANG.) and graded N+/N- source regions 22 to prevent disturbances due to band-to-band tunneling when the cell 12 is being erased.
As shown in FIG. 4A, the ETOX cell is written in the conventional EPROM manner. That is, hot electrons are injected from the graded source region 22 into the polysilicon (poly 1) floating gate 24 when the poly 2 word line 16 and the N+ bit line (drain) 14 are both high.
As shown in FIG. 4B, erasing the ETOX cell 12 is performed by Fowler-Nordheim tunneling of electrons from the floating gate 24 through the thin oxide 20 to the graded source region 22 when the source region 22 is high, the drain 14 is floating and the word line 16 is low. As stated above, the source 22 is graded to prevent junction breakdown during the erase operation.
As discussed by Verma et al, "Reliability Performance of ETOX Based Flash Memories", the programming of flash EPROM cells, such as the abovedescribed ETOX cell, may cause certain cell disturbances. Thus, an important consideration in the design of flash EPROM cells is the proper selection of read and programming voltages in order to minimize these disturbs.
The three principal flash EPROM cell disturbs that can occur during programming are DC erase, DC program and program disturb. These disturbs impact cells that share a common word line (row) or column with the cell being programmed.
DC erase occurs on programmed cells that are on the same word line as the cell being programmed. The programmed cells have electrons on their floating gates. During programming, the common word line is taken high, causing an electric field across the interpoly dielectric that may be large enough to cause electron flow from the poly 1 floating gate. This results in reduction of the threshold voltage of the programmed cells and can cause loss of data. That is, after a first cell in a row has been programmed, the subsequent programming of the remaining cells on the same row can cause the first cell to lose programming charge.
DC program occurs on unprogrammed or erased cells. These cells, having few electrons on their floating gates, have low threshold voltages. Increasing the voltages on the word lines of these cells creates high electric field across the cell tunnel oxide, resulting potentially in tunneling of electrons to the floating gate from the substrate, thereby increasing the cell's threshold voltage.
Program disturb occurs when a programmed cell that shares a column with a cell being programmed experiences a high electric field between its floating gate and drain. This can cause electrons to tunnel from the floating gate to the drain, thereby reducing the cell's threshold voltage.
Traditionally, reductions in flash EPROM array density have been accomplished by reducing the dimensions of the cell features in the photolithographic and etching procedures utilized in fabricating standard ETOX cells. The shrinking cell geometries resulting from these process developments have led to a need both for complex new isolation schemes for accommodating the reduced minimum cell pitch and for non-standard techniques for forming the many submicron contacts required in an ETOX array. (As stated above, and as shown in FIGS. 1 and 3, the conventional ETOX array architecture requires that the metal bit contact line 26 provide one drain contact 26a for each pair of ETOX cells 12.)
For example, Hisamune et al, "A 3.6 nm.sup.2 Memory Cell Structure for 16 mb EPROMs", IEDM 1989, pg. 583, disclose a process for minimizing EPROM cell pitch utilizing trench isolation of the bit lines and tungsten plugs for bit line contacts. Bergemont et al, "A High Performance CMOS Process for Sub-micron 16 mv EPROM", IEDM 1989, page 591, also disclose techniques for reducing the size of the standard T-shaped ETOX cell.
In another approach to flash EEPROM design, Intel's Flash Array Contactless EPROM (FACE) technology utilizes a buried N+ bit line to connect EPROM cell transistors. The metal bit line contacts the diffused buried N+ bit line every X cells (where X is typically 36 or 64) rather than utilizing the ETOX approach of one contact per two cells. See (1) B. J. Woo et al, "A Novel Cell Using Flash Array Contactless EPROM (FACE) Technology", IEEE IEDM 90 and (2) B. J. Woo et al, "A Poly-buffered FACE Technology For High Density Flash Memories", VLSI Symposium 1991.
Another way to avoid the special processing requirements associated with the fabrication of high density ETOX cell arrays is to use a cell which does not require the use of field oxide isolation and contacts in the array.
For example, U.S. patent application Ser. No. 539,657, filed by Boaz Eitan on Jun. 13, 1990 for EPROM VIRTUAL GROUND ARRAY, teaches a new contactless EPROM cell array and its associated process flow. Eitan's contactless concept is attractive because it allows high density EPROMs to be fabricated without using aggressive fabrication technologies and design rules.
The basic idea of the Eitan disclosure is the use of a "cross-point" EPROM cell, i.e. a cell which is defined by the crossing of perpendicular poly 1 floating gate and poly 2 word lines in a virtual ground array. In order to avoid drain turn, i.e. electron leakage from unselected cells on the same bit line as a selected cell, metal contacts silicon every two drain bit lines and the non-contacted source bit lines are connected to Vss only via an access transistor, as shown in FIGS. 5 and 6. Additionally, in the Eitan architecture, Each bit line is contacted once every 64 cells, each block of 64 cells on the same bit line constituting 1 segment. Thus, when programming a particular cell, only 1 64 cell segment need be addressed; all other segments are "off" and, therefore, the cells in these unselected segments are not susceptible to leakage.
However, there are several drawbacks associated with the Eitan process flow. First, five layers of processing are required over the poly 1 floating gate layer: oxide/nitride/oxide/poly cap/nitride. The poly 1 and the five overlying layers are defined twice, once at the poly 1 mask step and once at the poly 1 island mask step. These two etching steps are very critical because they define, respectively, the length and width of the EPROM cell. The requirement to etch more layers in these steps presents difficulties in controlling these critical dimensions. Also, failing to remove any one of the five layers presents the risk of poly 1 stringers along the edges of the field oxide. These edges are located in the neighborhood of the access transistors.
Furthermore, because the poly 2 word line in the Eitan array is not self-aligned with the poly 1 floating gate, a special "array field implant" is required to avoid leakage between adjacent bit lines. This leakage occurs when poly 2 is misaligned with poly 1. The poly 2 controls one part of the silicon and leads to a parasitic poly 2 transistor between adjacent bit lines. For this reason, a high threshold voltage is required to avoid the turn on of this parasitic poly 2 transistor. This is done using an array boron field implant.
In addition to the boron field implant, the Eitan process also calls for an "isolation oxide" to move the field threshold to a sufficiently high voltage. This field implant leads to boron lateral diffusion into the channel of the cell, leading to channel width reduction, high bit line loading and reduction of the bit line/substrate breakdown voltage.
Additionally, the poly 2 etch is very critical in the Eitan process. The poly 2 etching terminates on a poly cap. In order to maintain the coupling ratio, it is necessary to stop the etch within a nominal poly cap thickness. This is difficult from the point of view of overetched latitude with a thin poly cap layer. Depending on the thickness of the isolation oxide, poly 1 to poly 2 misalignment will affect the parasitic capacitance of the word lines.
Furthermore, removing the top nitride before depositing the poly 2 word line may affect the quality of the oxides all around the poly 1 floating gate. This could affect program disturb and data retention.
Thus, it would be highly desireable to have available a flash EPROM array that avoids the drawbacks of the Eitan array, eliminates the multi-contact limitations of the conventional T-cell ETOX array, but retains the drain turn-on immunity of the Eitan architecture.